I am trying to get my APU core to pass all of blargg's tests and am sooo close. I pass tests 1-10. But constantly get:
When I run 11.len_reload_timing.nes. I feel like I have tried everything I can think of at the moment.
Here's my general strategy for dealing with reloads at the moment. When $4003/$4007/$400b/$400f are written too. I do something to this effect:
So I don't actually do the reload yet, i just note that a reload was called for and record the value and when it happened.
Since, I am doing a lazy load, I need to perform the reload during status reads, no biggie
This also seems to work fine.
Finally, when the LC gets clocked, before I do any of the usual clocking logic, I do the reload with something like this:
Finally, here's a debug log of Square 0's LC reload activity during the test:
The value in the bracket will be either '=', '+', '-', or ' ' to indicate that the reload happened during, 1 cycle after, 1 cycle before or "other" respective to the clock.
The first number column is APU cycle $4003 was written on.
The second is the APU cycle that the clock happened on.
Finally, v is the value of the LC when clocked.
The one and only thing I can think of (which I will look into now) is if my lazy reload is making the status register return the wrong value during corner cases. But I don't see how that could happen since i *think*, the only time that would matter is if the LC was clocked on the same cycle as the status was read AND on the same cycle as the $4003 write, which is obviously not possible.
Anyone have any thoughts (Blargg, if you see this, your insights are usually awesome, so I'd love to hear your thoughts!)
thanks,
proxy
Quote:
4) Reload during length clock when ctr = 0 should work normally
When I run 11.len_reload_timing.nes. I feel like I have tried everything I can think of at the moment.
Here's my general strategy for dealing with reloads at the moment. When $4003/$4007/$400b/$400f are written too. I do something to this effect:
Code:
reload_value_ = length_table[index & 0x1f];
reload_ = true;
reload_cycle_ = nes::apu.cycle_count();
reload_ = true;
reload_cycle_ = nes::apu.cycle_count();
So I don't actually do the reload yet, i just note that a reload was called for and record the value and when it happened.
Since, I am doing a lazy load, I need to perform the reload during status reads, no biggie
Code:
if(reload_) {
value_ = reload_value_;
reload_ = false;
}
return value_;
value_ = reload_value_;
reload_ = false;
}
return value_;
This also seems to work fine.
Finally, when the LC gets clocked, before I do any of the usual clocking logic, I do the reload with something like this:
Code:
if(reload_) {
if((reload_cycle_ != nes::apu.cycle_count()) || (value_ == 0)) {
value_ = reload_value_;
}
reload_ = false;
}
if((reload_cycle_ != nes::apu.cycle_count()) || (value_ == 0)) {
value_ = reload_value_;
}
reload_ = false;
}
Finally, here's a debug log of Square 0's LC reload activity during the test:
Code:
RELOAD[ ]: 0: 14995 [v = 00]
RELOAD[-]: 44854: 44855 [v = 06]
RELOAD[ ]: 74776: 89697 [v = 00]
RELOAD[ ]: 89698: 89721 [v = 05]
RELOAD[=]: 134563: 134563 [v = 00]
RELOAD[ ]: 446814: 447757 [v = 00]
RELOAD[ ]: 893856: 895141 [v = 00]
RELOAD[ ]: 1340898: 1342525 [v = 00]
RELOAD[ ]: 1787940: 1789909 [v = 00]
RELOAD[-]: 44854: 44855 [v = 06]
RELOAD[ ]: 74776: 89697 [v = 00]
RELOAD[ ]: 89698: 89721 [v = 05]
RELOAD[=]: 134563: 134563 [v = 00]
RELOAD[ ]: 446814: 447757 [v = 00]
RELOAD[ ]: 893856: 895141 [v = 00]
RELOAD[ ]: 1340898: 1342525 [v = 00]
RELOAD[ ]: 1787940: 1789909 [v = 00]
The value in the bracket will be either '=', '+', '-', or ' ' to indicate that the reload happened during, 1 cycle after, 1 cycle before or "other" respective to the clock.
The first number column is APU cycle $4003 was written on.
The second is the APU cycle that the clock happened on.
Finally, v is the value of the LC when clocked.
The one and only thing I can think of (which I will look into now) is if my lazy reload is making the status register return the wrong value during corner cases. But I don't see how that could happen since i *think*, the only time that would matter is if the LC was clocked on the same cycle as the status was read AND on the same cycle as the $4003 write, which is obviously not possible.
Anyone have any thoughts (Blargg, if you see this, your insights are usually awesome, so I'd love to hear your thoughts!)
thanks,
proxy