http://utwired.engr.utexas.edu/rgd1/index.cfm (just look at ohms law)
http://en.wikipedia.org/wiki/Transistor ... stor_logic
http://en.wikipedia.org/wiki/IC_power_supply_pin (think of chips as resistors in parallel, the more chips you add, the more current is drawn)
http://en.wikipedia.org/wiki/Computer_bus
http://en.wikipedia.org/wiki/Address_bus
http://en.wikipedia.org/wiki/Control_bus
http://webster.cs.ucr.edu/AoA/Windows/H ... ation.html
http://www.play-hookey.com/digital/ (d latches and flip flops)
http://www.chrisward.uklinux.net/6502/circuit.shtml (6502 specifics)
I think if you skim through these links in order it should help.
I would recommend looking at a EPROM datasheet, but you first need to understand binary decoders:
http://www.asic-world.com/digital/combo2.html
and tri-state gates:
http://www.cs.umd.edu/class/sum2003/cms ... state.html
Beyond the power rails, typical pins on an EPROM and SRAM memory (for simplicity's sake) are address pins, data pins and control pins.
A0-n = address lines, these connect to the CPU's address lines. When the CPU wants to read or write a specific address it puts the binary address on these pins. A0 is the least significant bit of the address.
D0-n = data lines, these connect to the CPU's data lines. When the CPU reads or writes, it either puts data on these lines or takes data from these lines.
/CE = chip enable, if this signal is not active, the ROM/RAM/device will not interact with the bus (it's data pins will be in "high impedance" [resistance] making the chip disconnected so it won't interfere with other devices that are actually supposed to "talk" or "listen".) Generally this signal is enabled by a decoder. The decoder takes the CPU's address lines as inputs and outputs enables according to how the system designer wants the memory map.
/OE = output enable, this should be attached to the CPU's /read signal. When the CPU intends to read from an address, it will first put out the address, then assert (enable) the /read signal. Since this is connected to /OE, it will cause the ROM/RAM to output whatever is at that address location if the ROM/RAM is chip enabled, then after a specific time, the CPU will itself latch whatever is on the bus.
/WE = write enable, this should be attached to the CPU's /write signal. This is the opposite of /OE, when the CPU wants to write something, it first puts out the address and data, then asserts /WE for the RAM/register/device to latch in the data (if the device is chip enabled.)
VPP = a special programming voltage necessary to blow fuses in an EPROM array (turn the memory bits into a 0)