MMC1 free implementation on CPLD released

I just finished developing a MMC1 mapper clone, running successfully on a Xilinx XC9572 CPLD and a SNROM PCB (Kid Icarus/Metroid).
All features are supported except 32 kb PGR ROM bank size.
WRAM write can be enabled and disabled at any time (starts in enable state)
Mapper powers-up with all registers in reset state, except control register, which starts with all bits set ($C000-$FFFF fixed bank, 16 Kb PGR bank size).
This allows access to interupt vectors at the end of the program ROM.

I released the source code (VHDL) as open-source under GPL license.
I just wanted to share it with you all.

You can find information on the English section of my web:
http://www.consolasparasiempre.net/english/english.php

or, if you speak Spanish:
http://www.consolasparasiempre.net/proy ... yectos.php

I'm still documenting and preparing some pictures and video.
I'll upload some pictures soon in the forum.

Thanks for sharing, lots of great info on the website too!

Cool !
Adding 32kb switching should be fairly trivial, too.

How many macrocells would a subset supporting only 8K CHR ROM switching (no CHR mode bit in $8000, no $C000 at all) take? That'd be a useful subset to get SNROM/SUROM/SXROM going.

Interesting cutdown here
It seems that such a MMC1 would fit in the smaller XC9536 CPLD, as it requires only 33 macrocells.
This will be fine for my test games Kid Icarus and Metroid, and maybe for Zelda.



Sure it will. But as I want to make a "ready to go" solution, not just theorical, that means I would have to get time to find a game which uses that kind of configuration, and test it to see if it works.
If anyone is interested, I can implement a full MMC1, but is up to him/her to test the 32kb bank functionality.

You should be able to further shrink the number of macrocells required by combining the state machine into the shift register, as tepples and I outlined here.

I did actually try that and was successful. I was able to get the entirety of the SNROM including CHR-A16 WRAM disabling to fit within 36Mcells.

By "game" do you mean a commercial game licensed by Nintendo, or is a test ROM fine too? If a test ROM is fine too, you could try building the Forbidden Four multicart (wiki page; BBS topic). Successfully launching SMB1 relies on 32K mode support. Or if you want, I could make a special build of Action 53 (wiki page; BBS topic) designed for MMC1's 32K mode instead of BNROM.

greate!

My approach was not to fully optimize the design, with somekind of commercial mind, but try to make it very clear, more with an educational idea in mind.
Anyway, I just created a new more optimized architecture, leaving out the state machine, using 5-bit shift register, and using simpler registers (no reset signals), and I still get 42 macrocells for full MMC1 (still, no 32kb ROM bank support).
For me, it just doesn't worth it, as I'm not trying to put many mappers into a CPLD, and XC9572 isn't too much expensive than a XC9536.

Anyway, if there's someone out there who has done it using less than 36 macrocells, I'd love to see the source, if he/she is willing to share it.



Have you done it? A full MMC1?
I can get it fit in about 30 Mcells too if I remove CHR banking, and just get basic functions for a SNROM.



The problem is that I have no rewrittable cart for NES at the moment (I plan to make one sooner or later).

I'll share my sources with you. Let me clean some things up and I'll send you a PM.


A full SNROM, not a full MMC1. SNROM doesn't use CHR-ROM A13-15 pins, I was able to fit it within 36Mcells on a XC9536XL. Note, it sounds like you're using the 5volt variant (non-XL), and I'm using the 3.3v XL family (5v tolerant) because it hasn't been discontinued like the non-XL family. I believe there are some minor internal differences between the two as well because I once synthesized something for the non-XL that wouldn't fit. I then switched over to the XL equivalent and it DID fit, I could have had something messed up in my settings that explains the differences in my findings though.

Maybe optimizing it as much as possible is still a good idea though, provided you can make it clear enough how each part works and interacts with the other parts. I guess that the best optimizations are those that simplify the circuit though (take up less space and are easier to understand).


What kind of register is that? o_O

It's a "shit register" because it makes bank switching so slow just to save three pins.

What kind of register is that? o_O

What do you mean by "what kind"?
A shift register, to build a parallel output from a serial input.
As MMC1 internal registers are 5 bit wide, the shit register must be 4 bit (if using a state machine to generate load control signal) or 5 bit wide (if using one of those bits as a mechanism to generate load signal).

edit: I see I wrote "shit" instead of "shift". I didn't even notice it the second time!

It was a joke since he typo'd shift to shit.

Hi, game Treasure master and Ninja Gaiden work for you?

I hang these games. Chip and Dale works without problems

What do you mean?

All games start, I solved the problem

What games use 32 kb PGR ROM bank size?

Among carts that use MMC1 in the normal mapper #1 configuration (no funny stuff like NES-EVENT), these are most likely to use 32 KiB banks: The Forbidden Four multicart uses 32 KiB PRG banks when running SMB1. I imagine that SMB1/Duck Hunt/World Class Track Meet (a bunch of NROM/CNROM games hacked to MMC1) and one of the versions of RC Pro-Am (which was produced on both AN1ROM and SEROM boards) use 32 KiB banks as well.

What was the issue? (don't make other people rage)

Heh, few things are more frustrating than finding an old thread where someone had the exact same problem you're having now and the last reply is from the same person and says only "Solved.", without any sort of explanation.

I'm sorry, game Treasure master and Ninja Gaiden did not work with the new MMC1. But after I put the resistor is 100 ohms per signal M2 or F2 - the problem is gone. Game Chip and Dale worked fine without a resistor.



"Chip and Dale works without problems" - Chip and Dale works fine.

Chip and Dale 1
Chip and Dale 2
Yo Noid
Tale Spin
Castlevania 2
Darkwing Duck
Ninja Gaiden
Adventures in the Magic Kingdom

These games work.


RoboCop 3 is not running.

tell me why it is not working?

Sorry to necro another post...but it's better than starting a new one.

Does anyone still have the files that patroclus originally posted here for the MMC1 CPLD? I had sent him a PM a couple months ago, but it seems like he no longer frequents here. If someone could relink them or send me a PM that would be awesome

Try to use Wayback Machine to download the files.

Sorry to necro this post again, but I was looking through the code for this mapper and I was wondering how much would it take to enable 32kb banking? The OP said that he never enabled it, but I've been looking through his code wondering where that would get inserted. I've been fiddling around with some basic CPLD designs, but they've all been built with schematics and not VHDL...so I can't quite grasp it.

TL;DR - What code would have to be inserted to this mapper to enable 32kb PRG bankswitching?