I'm getting some rough idea of how the OAM DRAM works (for reads anyway). Does the following sound correct?
- During the first phase, the bitlines are charged by opening up the transistors on the right-hand side to current using pclk0. At the end of this phase, pclk0 goes low, disconnecting power, but the bitlines remain charged through capacitance.
- During the second phase, the now-charged bitlines are connected to the row of memory cells holding the bits to be read by opening up the corresponding spr_rowx line. Additionally, the spr_colx line corresponding to the bits to be read is open at this point, and the value that's let through is the value returned by the read.
Additionally, the charged bitlines will help charge up the memory cells on the row that was "opened" (connected to the bitlines), preventing them from fading. This works by charging up the side of the memory cell that was high, while current on the other side will just drain to ground (since the high side will open up a pull-down transistor for the other side).
(Things get a bit confusing since a "row" in Visual 2C02 actually has vertical orientation
)
Edit: Looks like the pclk0 connection on the right isn't actually used in the simulator, so that no "pre-charging" of the bitlines happens. Clicking on the gates shows that there's no transistors there (though the visual display when nothing is selected is as-if there would be transistors there). Then the following comments on IRC make sense:
Code:
01:45 < _Q> in visual2c02, the bus precharge lines aren't actually connected
01:45 < _Q> I manually deleted all of the transistors
01:45 < _Q> in the real chip, they're necessary
01:45 < _Q> but in the simulator, they cause timing glitches that destroy the data in the DRAM