This is a question for folks familiar with EE enough that they hopefully understand what I'm talking about. :-)
On lots of classic consoles, memory-mapped registers tend to have multiple functions broken down into whatever bits are sent across the (data?) bus at that time. I'm referring to something like the NES/Famicom's PPUCTRL/$2000 register, where there are literally 7 different features/capabilities split across 8 bits.
My question is: why is (or was?) it done this way? I'll expand on what I'm asking below.
It's fairly obvious there was quite a lot of addressing space left over (look at $2008 to $3fff), so I've always wondered why there wasn't separate memory-mapped registers given to each feature. For example, why not 7 different memory-mapped registers, i.e.:
$2000 = Base table name address (D1-D0)
$2001 = VRAM address increment mode (D0)
$2002 = Sprite pattern table address (D0)
$2003 = Background pattern table address (D0)
$2004 = Sprite size (D0)
$2005 = PPU master/slave select (D0)
$2006 = Generate NMI at start of VBlank (D7)
Is there something about doing it the former way that makes it easier for the designer? Does it save on parts, "circuit space", design costs, etc. somehow?
This isn't limited to consoles either, lots of super I/O chips (which I write software for, via I2C and SMBus) operate this way too; it's fairly universal.
Just curious why it's done the way it is and not the way shown in my above example. :-)
Note: I want to be clear here (this is for you psychopathicteen ;P Hahaha) -- I am not complaining; I really couldn't care less which method is used, as I've worked with so many different microcontrollers and chips that it's just second nature to keep track using temporary RAM variables and AND/OR'ing out what you want/don't want. I'm just wondering about the reasoning/design.
On lots of classic consoles, memory-mapped registers tend to have multiple functions broken down into whatever bits are sent across the (data?) bus at that time. I'm referring to something like the NES/Famicom's PPUCTRL/$2000 register, where there are literally 7 different features/capabilities split across 8 bits.
My question is: why is (or was?) it done this way? I'll expand on what I'm asking below.
It's fairly obvious there was quite a lot of addressing space left over (look at $2008 to $3fff), so I've always wondered why there wasn't separate memory-mapped registers given to each feature. For example, why not 7 different memory-mapped registers, i.e.:
$2000 = Base table name address (D1-D0)
$2001 = VRAM address increment mode (D0)
$2002 = Sprite pattern table address (D0)
$2003 = Background pattern table address (D0)
$2004 = Sprite size (D0)
$2005 = PPU master/slave select (D0)
$2006 = Generate NMI at start of VBlank (D7)
Is there something about doing it the former way that makes it easier for the designer? Does it save on parts, "circuit space", design costs, etc. somehow?
This isn't limited to consoles either, lots of super I/O chips (which I write software for, via I2C and SMBus) operate this way too; it's fairly universal.
Just curious why it's done the way it is and not the way shown in my above example. :-)
Note: I want to be clear here (this is for you psychopathicteen ;P Hahaha) -- I am not complaining; I really couldn't care less which method is used, as I've worked with so many different microcontrollers and chips that it's just second nature to keep track using temporary RAM variables and AND/OR'ing out what you want/don't want. I'm just wondering about the reasoning/design.