How do mapper chips actually work?

This is a general operation question about chip behavior for something like bankswitching. I get the usage of writing to a port/address, and that makes a certain chunk of memory accessible by the cpu and all that. What maintains that state after I make that selection?

For example, looking at UNROM, there are some discrete logic chips for prg banking. I can select a bank number and write it to $8000 (or other suitable address, glossing over details) to map in the prg data I want. As I understand it the bits for that bank number on the corresponding data lines are input for the discrete chips, and the output is tied to the high address lines on the prg rom. So far so good. What happens at the next instructions when I want to read something out of the new prg bank? The bank number value is no longer on the bus right? What keeps the outputs to the high address lines fixed to what I want?

Using the same example of UNROM, you'll see that there's two ICs: a 74'32 quad OR gate (which is what makes the upper 16 KiB of the address space stay mapped as the upper 16 KiB) and a 74'161 4-bit latch and counter.

That latch is what keeps track of what bank was written. Wikipedia explains how the latch itself works: wikipedia:Flip-flop (electronics)#D flip-flop

So in that example, the output value is set when /LOAD is low (or whichever control pin manages that)? And then it keeps that value until its told to change again?

For something like MMC3, it has a similar device built in?

Yeah, the 74'161 is connected with /LOAD to R/W and ↑CLOCK to /ROMSEL, so the value is latched when /ROMSEL goes high (at the end of the cycle where the write happens).

And, yes, the MMC3 has something equivalent ... or a lot of somethings equivalent, anyway.

Cool, that all makes sense. Thank you very much.