Does anyone have an FDS and an oscilloscope or logic analyzer? I'm curious about several completely unimportant aspects of its DRAM controller.
Things like:
/RAS-only refresh? or /CAS-before-/RAS refresh? or Hidden refresh? (or NO refresh??)
How do CPU A0-A14 map through the multiplexers?
What selects between the two /CAS lines?
Things like:
/RAS-only refresh? or /CAS-before-/RAS refresh? or Hidden refresh? (or NO refresh??)
How do CPU A0-A14 map through the multiplexers?
What selects between the two /CAS lines?