I got some interesting carts recently so I thought of sharing them, as the design is quite rare & interesting.
1. Don Doko Don 3
Game:
Don Doko Don 3 (Dok Doko Don 2 hack)
My comments:
* It is mapper 33 with mirroring register moved from $8000.6 to $e000.6
* Quite elegant hardware solution - everything stored in 74*670, while combinatorial logic is provided by PAL. Also, one bit of mirroring which should be packed somewhere is stored in PAL.
2. Dragon Ball Z 2
Game: Dragon Ball Z 2 (ported from Bandai 24C02)
One of the very few games that uses VRC2+DIP8 EPROM. AX5705 is VRC2 (this chip can also be seen under name 23C269 which also has functional EPROM lines)
Due to different time of changing ROMSEL/M2, they added circuit for delaying rising edge of M2.
PAL has 3 latches so research is in progress.
3. Don Doko Don
Game:
Don Doko Don (ported from mapper 33 to VRC2)
Mapper:
VRC2
PRG-ROM: 128 kB
CHR-ROM: 256 kB
My comments:
There is additional 2 kB ROM mapped at $6000-$7fff (only A0-A9 wired). It is some kind of patch,
that game jumps and executes code from here (probably modified routine to switch bank,
which cannot be modified in original rom due to insufficient free space)
4. Dragon Ball Z 3
Same situation like with Dragon Ball Z2, but the way they enhances VRC2 this time to be quite different. Also, some of PRG/CHR lines are reversed. They also ommited the M2 delaying circuit (but this PCB I saw previously on this forum which HAS this circuit)
PAL has latches so research is in progress.
1. Don Doko Don 3
Game:
Don Doko Don 3 (Dok Doko Don 2 hack)
My comments:
* It is mapper 33 with mirroring register moved from $8000.6 to $e000.6
* Quite elegant hardware solution - everything stored in 74*670, while combinatorial logic is provided by PAL. Also, one bit of mirroring which should be packed somewhere is stored in PAL.
Code:
---------------------------------PAL-------------------------------------------
Automatic analysis:
!REG2GR! <= (!PPU-A12);
CIRAM-A10 <= (CPU-D6 & PPU-A11) | (!CPU-D6 & PPU-A10);
O2 <= (I12); //unused input
O3 <= Probably non-combinatorial
!REG2GW! <= (!CPU-A13) | (CPU-!ROMSEL!) | (CPU-R/!W!) | (CPU-A14);
!REG1GW! <= (!CPU-A1) | (CPU-!ROMSEL!) | (CPU-R/!W!) | (CPU-A14) | (CPU-A13);
!REG0GW! <= (CPU-!ROMSEL!) | (CPU-R/!W!) | (CPU-A1) | (CPU-A14) | (CPU-A13);
PRG-!CE! <= (!CPU-R/!W!) | (CPU-!ROMSEL!);
Additional manual analysis for feedback looped outputs:
O3 <= CPU-D6 when CPU-!ROMSEL!=0 and CPU-R/!W=0 and CPu-A13=1 and CPU-A14=1 and CPU-A1=0 and CPU-A0=0
CIRAM-A10 <= PPU-A10 when O3='0' else PPU-A11
---------------------------------MEMORY MAP------------------------------------
PRG-ROM: 128 kB
CHR-ROM: 256 kB
Bus conflicts: no
CPU:
$8000|$a000|$c000|$e000
-----+-----+-----+-----
$8000|$8001| -1
PPU:
$0000|$0400|$0800|$0c00|$1000|$1400|$1800|$1c00
-----+-----+-----+-----+-----+-----+-----+-----
$8002 | $8003 |$a000|$a001|$a002|$a003
---------------------------------REGISTERS-------------------------------------
[....pppp] $8000/$8001 [mask: $e003]
||||
++++- 8 kB PRG at $8000-$9fff/$a000-$bfff
[.ccccccc] $8002/$8003 [mask: $e003]
|||||||
+++++++- 2 kB CHR at $0000-$07ff/$0800-$0fff (lowest bit is NOT ignored)
[cccccccc] $a000/$a001/$a002/$a003 [mask: $e003]
||||||||
++++++++- 1 kB CHR at $1000-$13ff/$1400-$17ff/$1800-$1bff/$1c00-$1fff
[.m......] $e000 [mask: $e003]
|
+------- mirroring (0=V, 1=H)
-------------------------------------------------------------------------------
Automatic analysis:
!REG2GR! <= (!PPU-A12);
CIRAM-A10 <= (CPU-D6 & PPU-A11) | (!CPU-D6 & PPU-A10);
O2 <= (I12); //unused input
O3 <= Probably non-combinatorial
!REG2GW! <= (!CPU-A13) | (CPU-!ROMSEL!) | (CPU-R/!W!) | (CPU-A14);
!REG1GW! <= (!CPU-A1) | (CPU-!ROMSEL!) | (CPU-R/!W!) | (CPU-A14) | (CPU-A13);
!REG0GW! <= (CPU-!ROMSEL!) | (CPU-R/!W!) | (CPU-A1) | (CPU-A14) | (CPU-A13);
PRG-!CE! <= (!CPU-R/!W!) | (CPU-!ROMSEL!);
Additional manual analysis for feedback looped outputs:
O3 <= CPU-D6 when CPU-!ROMSEL!=0 and CPU-R/!W=0 and CPu-A13=1 and CPU-A14=1 and CPU-A1=0 and CPU-A0=0
CIRAM-A10 <= PPU-A10 when O3='0' else PPU-A11
---------------------------------MEMORY MAP------------------------------------
PRG-ROM: 128 kB
CHR-ROM: 256 kB
Bus conflicts: no
CPU:
$8000|$a000|$c000|$e000
-----+-----+-----+-----
$8000|$8001| -1
PPU:
$0000|$0400|$0800|$0c00|$1000|$1400|$1800|$1c00
-----+-----+-----+-----+-----+-----+-----+-----
$8002 | $8003 |$a000|$a001|$a002|$a003
---------------------------------REGISTERS-------------------------------------
[....pppp] $8000/$8001 [mask: $e003]
||||
++++- 8 kB PRG at $8000-$9fff/$a000-$bfff
[.ccccccc] $8002/$8003 [mask: $e003]
|||||||
+++++++- 2 kB CHR at $0000-$07ff/$0800-$0fff (lowest bit is NOT ignored)
[cccccccc] $a000/$a001/$a002/$a003 [mask: $e003]
||||||||
++++++++- 1 kB CHR at $1000-$13ff/$1400-$17ff/$1800-$1bff/$1c00-$1fff
[.m......] $e000 [mask: $e003]
|
+------- mirroring (0=V, 1=H)
-------------------------------------------------------------------------------
2. Dragon Ball Z 2
Game: Dragon Ball Z 2 (ported from Bandai 24C02)
One of the very few games that uses VRC2+DIP8 EPROM. AX5705 is VRC2 (this chip can also be seen under name 23C269 which also has functional EPROM lines)
Due to different time of changing ROMSEL/M2, they added circuit for delaying rising edge of M2.
PAL has 3 latches so research is in progress.
3. Don Doko Don
Game:
Don Doko Don (ported from mapper 33 to VRC2)
Mapper:
VRC2
PRG-ROM: 128 kB
CHR-ROM: 256 kB
My comments:
There is additional 2 kB ROM mapped at $6000-$7fff (only A0-A9 wired). It is some kind of patch,
that game jumps and executes code from here (probably modified routine to switch bank,
which cannot be modified in original rom due to insufficient free space)
4. Dragon Ball Z 3
Same situation like with Dragon Ball Z2, but the way they enhances VRC2 this time to be quite different. Also, some of PRG/CHR lines are reversed. They also ommited the M2 delaying circuit (but this PCB I saw previously on this forum which HAS this circuit)
PAL has latches so research is in progress.