8in1 multicart - NESdev BBS

8in1 multicart
by v5100v5100 on 2019-10-15 (#243207)

Hello, everyone.I have an 8in1 card, but it doesn't work properly. The problem is that the menu can be displayed normally, and the game cannot start when the game is selected.I made a simple analysis of it with the help of the programmer and kazzo and came to the following conclusions:

1.U1 is 27C257, which has stored the menu program. I have extracted it in the attachment.
U6 is 6264.
U8 is 74LS174.
U9 is GAL16V8.
U11 is 74LS139.
2.I tried to program dump GAL16V8 data, but failed.Except GAL16V8, all the other IC and components I tested were normal.

Therefore, I think GAL16V8 is damaged. If GAL16V8 is damaged, the solution I have in mind is to deduce the equation of GAL16V8 according to the existing circuit and menu program or replace GAL16V8 with multiple 74XXX combinations.So I want you to help me solve this problem.

Thank you very much!

Re: 8in1 multicart
by krzysiobal on 2019-10-16 (#243208)

Code:

Presumable order of ROM chunks:
  PRG: 512 kB ROM (U2) + 512 kB ROM (U3) + 32 kB ROM (U1) + 8 kB RAM (U5, not soldered)
  CHR: 512 kB ROM (U10) + 512 kB ROM (U4) + 8 kB RAM (U6)
  
[...A.BCD] $6000-$7fff - control register, set to 0 on powerup/reset
    | |||
    | ||+-- PRG/CHR-A17
    | |+--- PRG/CHR-A18
    | +---- PRG/CHR-A19
    +------ ROM selection: 0=ROM with MENU U1, 1=ROMs with games (U2+U3)
    +------ might also block further writes to this reg when set to 1 (needs pal analysis for confirmation)
  
PRG A16-A13: controlled by MMC3
PRG A17: controlled by PAL (can come from MMC3-PRG-A17 or from PAL)
PRG A18 = C
PRG A19 = B

CHR A16-A10: controlled by MMC3
CHR A17: controlled by PAL (can come from MMC3-PRG-A17 or from PAL)
CHR A18 = C
CHR A19 = B

Doubts:
* I don't see any bit determining if CHR-ROM or CHR-RAM should be applied.
  Maybe it's hardcoded that for  menu (REG=%00000) and for position 3 (REG=%10010)
  it should enable RAM, otherwise ROM
* I don't see any bit determining if PRG A17/CHR A17 should come from MMC3 (bank size 256 kB)
  or from PAL (bank size 128 kB)
* PAL's pin 18/19 are shorted
* Why PAL needs MMC3-PRG-!CE pin, if it already has wired CPU-!ROMSEL and CPU-R/!W?

                     PRG-ROM | PRG-RAM | CHR-ROM | CHR-RAM |  $6000 
0. Menu            |   32 kB |       0 |       0 |    8 kB | %00000 (relies on powerup value )
1. Super Contra    |  128 kB |       0 |  128 kB |       0 | %10000
2. Ninja Gaiden 2  |  128 kB |       0 |  128 kB |       0 | %10001
3. Contra          |  128 kB |       0 |       0 |    8 kB | %10010
4. Double Dragon 2 |  128 kB |       0 |  128 kB |       0 | %10011
5. Kage            |  128 kB |       0 |  128 kB |       0 | %10100
6. Ninja Gaiden 3  |  128 kB |       0 |  128 kB |       0 | %10101
7. Double Dragon 3 |  128 kB |       0 |  128 kB |       0 | %10110
8. Dead Fox        |  128 kB |       0 |  128 kB |       0 | %10111

                .--v--.
MMC3_PRG_nCE -> |01 20| -- VCC
          M2 -> |02 19| -> CHR_RAM_CS
 CPU_nROMSEL -> |03 18| -> CHR_RAM_CS
     CPU_A14 -> |04 17| <- CPU_RnW
     CPU_A13 -> |05 16| -> CHR_A17
      REG_D4 -> |06 15| -> CHR_RAM/nROM
      REG_D2 -> |07 14| <- MMC3_CHR_A17
      REG_D1 -> |08 13| -> PRG A17
      REG_D0 -> |09 12| -> REG_nWR
         GND -- |10 11| <- MMC3_PRG_A17
                '-----'
                  PAL
              
REG_nWR <= 0 when CPU_nROMSEL=1 and M2=1 and CPU_A14=1 and CPU_A13=1 and CPU_RnW=0 else 1

If that's PAL failure, you can replace it with fresh new pre-programmed GAL.
But I'd check first U8.pin 1 voltage when cartridge is running (you don't have to solder all elements, just 74174, diode/resistor and capacitor).

Re: 8in1 multicart
by v5100v5100 on 2019-10-16 (#243212)

krzysiobal wrote:

Code:

Presumable order of ROM chunks:
  PRG: 512 kB ROM (U2) + 512 kB ROM (U3) + 32 kB ROM (U1) + 8 kB RAM (U5, not soldered)
  CHR: 512 kB ROM (U10) + 512 kB ROM (U4) + 8 kB RAM (U6)
  
[...A.BCD] $6000-$7fff - control register, set to 0 on powerup/reset
    | |||
    | ||+-- PRG/CHR-A17
    | |+--- PRG/CHR-A18
    | +---- PRG/CHR-A19
    +------ ROM selection: 0=ROM with MENU U1, 1=ROMs with games (U2+U3)
    +------ might also block further writes to this reg when set to 1 (needs pal analysis for confirmation)
  
PRG A16-A13: controlled by MMC3
PRG A17: controlled by PAL (can come from MMC3-PRG-A17 or from PAL)
PRG A18 = C
PRG A19 = B

CHR A16-A10: controlled by MMC3
CHR A17: controlled by PAL (can come from MMC3-PRG-A17 or from PAL)
CHR A18 = C
CHR A19 = B

Doubts:
* I don't see any bit determining if CHR-ROM or CHR-RAM should be applied.
  Maybe it's hardcoded that for  menu (REG=%00000) and for position 3 (REG=%10010)
  it should enable RAM, otherwise ROM
* I don't see any bit determining if PRG A17/CHR A17 should come from MMC3 (bank size 256 kB)
  or from PAL (bank size 128 kB)
* PAL's pin 18/19 are shorted
* Why PAL needs MMC3-PRG-!CE pin, if it already has wired CPU-!ROMSEL and CPU-R/!W?

                     PRG-ROM | PRG-RAM | CHR-ROM | CHR-RAM |  $6000 
0. Menu            |   32 kB |       0 |       0 |    8 kB | %00000 (relies on powerup value )
1. Super Contra    |  128 kB |       0 |  128 kB |       0 | %10000
2. Ninja Gaiden 2  |  128 kB |       0 |  128 kB |       0 | %10001
3. Contra          |  128 kB |       0 |       0 |    8 kB | %10010
4. Double Dragon 2 |  128 kB |       0 |  128 kB |       0 | %10011
5. Kage            |  128 kB |       0 |  128 kB |       0 | %10100
6. Ninja Gaiden 3  |  128 kB |       0 |  128 kB |       0 | %10101
7. Double Dragon 3 |  128 kB |       0 |  128 kB |       0 | %10110
8. Dead Fox        |  128 kB |       0 |  128 kB |       0 | %10111

                .--v--.
MMC3_PRG_nCE -> |01 20| -- VCC
          M2 -> |02 19| -> CHR_RAM_CS
 CPU_nROMSEL -> |03 18| -> CHR_RAM_CS
     CPU_A14 -> |04 17| <- CPU_RnW
     CPU_A13 -> |05 16| -> CHR_A17
      REG_D4 -> |06 15| -> CHR_RAM/nROM
      REG_D2 -> |07 14| <- MMC3_CHR_A17
      REG_D1 -> |08 13| -> PRG A17
      REG_D0 -> |09 12| -> REG_nWR
         GND -- |10 11| <- MMC3_PRG_A17
                '-----'
                  PAL
              
REG_nWR <= 0 when CPU_nROMSEL=1 and M2=1 and CPU_A14=1 and CPU_A13=1 and CPU_RnW=0 else 1

If that's PAL failure, you can replace it with fresh new pre-programmed GAL.
But I'd check first U8.pin 1 voltage when cartridge is running (you don't have to solder all elements, just 74174, diode/resistor and capacitor).

Attachments is my dump ROM files.

Your reply has been very helpful.The third game Contra, is a 256KB game converted to Mapper4 using the Japanese version of Contra. According to your tips, the menu without soldered U9(GAL16V8) works normally but cannot select the game, and the menu after soldered U9(GAL16V8) does not work normally and nothing is displayed on the screen.So I think the U9 is damaged.But I didn't have the ability to write equations for GAL16V8.Can you help me write the final GAL equations?If you can, thank you very much!

Re: 8in1 multicart
by lidnariq on 2019-10-16 (#243214)

krzysiobal wrote:

* PAL's pin 18/19 are shorted

In 16V8 "Complex" mode, pin 19 is output-only (but can be tristated), while pin 18 can be used as an input (when tristated). But I can't see any reason why the fitter wouldn't've instead put the same signal on pin 18 instead of externally connecting pin 19 to pin 18's foldback.

Maybe it's using the per-pin tristate control? Perhaps pins 18 and 19 divided some logic that's too complex for a single 7OR?

Re: 8in1 multicart
by krzysiobal on 2019-10-16 (#243216)

Try that:

Another weird thing is that:
* PAL.15 controls whether CHR-ROM is enabled (0) or disabled (1),
* PAL.18/19 controls whether CHR-RAM is enabled (1) or disabled (0).
No idea why they separated this into 2 pins. This way there can be also bus conflct or open bus when the value on those pins differ.

Re: 8in1 multicart
by NewRisingSun on 2019-10-16 (#243217)

Ninja Gaiden 3 (in U3.BIN) seems to be corrupt.

Emulating this mapper is not too difficult, and I would propose NES 2.0 Mapper #392 for it. One question remains in this context: should the 32 KiB of menu ROM (chip U1) be at the start or at the end in the NES ROM file's PRG section? Start would make sense because it's what appears with the corresponding bit in the "0" position, but end might be better because one could switch between ROM chips with OR instead of an addition.

Supervision 16-in-1 has a similar problem. In UNIF format, the menu ROM is PRG1, but in NES format (mapper #53), the menu is at the beginning.

Re: 8in1 multicart
by v5100v5100 on 2019-10-16 (#243220)

krzysiobal wrote:

Try that:

Another weird thing is that:
* PAL.15 controls whether CHR-ROM is enabled (0) or disabled (1),
* PAL.18/19 controls whether CHR-RAM is enabled (1) or disabled (0).
No idea why they separated this into 2 pins. This way there can be also bus conflct or open bus when the value on those pins differ.

You are wonderful!
I failed to erase with the current GAL16V8, and failed to program.It looks like GAL16V8 is completely damaged.I will buy the new GAL16V8 later to program your equations. Thanks again.

Re: 8in1 multicart
by v5100v5100 on 2019-10-16 (#243221)

NewRisingSun wrote:

Ninja Gaiden 3 (in U3.BIN) seems to be corrupt.

Emulating this mapper is not too difficult, and I would propose NES 2.0 Mapper #392 for it. One question remains in this context: should the 32 KiB of menu ROM (chip U1) be at the start or at the end in the NES ROM file's PRG section? Start would make sense because it's what appears with the corresponding bit in the "0" position, but end might be better because one could switch between ROM chips with OR instead of an addition.

Supervision 16-in-1 has a similar problem. In UNIF format, the menu ROM is PRG1, but in NES format (mapper #53), the menu is at the beginning.

Supervision 16-in-1? Is this ROM file attached?

Re: 8in1 multicart
by NewRisingSun on 2019-10-16 (#243226)

Yes

Re: 8in1 multicart
by v5100v5100 on 2019-10-17 (#243229)

krzysiobal wrote:

Try that:

Another weird thing is that:
* PAL.15 controls whether CHR-ROM is enabled (0) or disabled (1),
* PAL.18/19 controls whether CHR-RAM is enabled (1) or disabled (0).
No idea why they separated this into 2 pins. This way there can be also bus conflct or open bus when the value on those pins differ.

After using your write GAL16V8 equations reprogramming,problem fixed,the card can work normally. Thank you very much!