kyuusaku wrote:
Another scrolling background is doable with the block RAM.
Ah, yeah, I forgot about that. I would assume that the block RAM would be for CHR-RAM in this case, correct?
Quote:
-background sprites
Like the tile-based "sprites" in most MSX games? That would be interesting, since on an NES, these "sprites" could do smooth vertical scrolling while the BG objects in many MSX games usually do not. But horizontally scrolling would still need to be choppy.
Quote:
-virtual framebuffer -> CHR RAM mapper
I assume this is about the block RAM... or are you talking about the regular CHR-RAM? The lack of pin access for the FPGA makes this a bit tricky. Perhaps the mapper could generate code of an unrolled loop to the CPU. It could save the PC, feed LDA $whatever, STA $2007 for a number of times, then feed a JMP back to the saved PC.
This brings back the CPU optimization idea I had. Note that all of this CPU optimization can only be done while PRG is executed, not the NES stock RAM. Here's an example of the mapper making an indirect JSR out of an illegal instruction, and optimizing an RTS into a JMP:
Code:
KIL ;$02
db <lookup, >lookup
;When the mapper fetches $02 as an opcode from the PRG-RAM data bus, it'll save the PC to block RAM, disable PRG-RAM for that byte, and feed the CPU bus with $6C, turning it into:
JMP (lookup) ;lookup points to "routine"
routine:
...
RTS
;When the mapper fetches $60 as an opcode from the data bus, it'll restore the PC from block RAM, disable PRG-RAM, and feed instead:
JMP saved_PC
Hopefully, that's clarified better. The generation of unrolled loops by the mapper could also be an interesting expansion as well. They must be planned so that the PC will not overflow to zero page. Here's an example with writes from CPU $0300-$04FF to PPU $2000-$21FF via $2007:
Code:
LDA #$20
STA $2006
LDA #$00
STA $2006
LDA #$01 ;high byte of block size
STA highblock ;mapper register
LDA #$FF ;low byte of block size
STA lowblock ;mapper register
LDA #$03 ;high byte of address to read
STA highaddr ;mapper register
LDA #$00 ;low byte of address
STA low addr
STA write_to_2007 ;next instruction is at "saved_PC"
;at this point, the mapper would save the PC and feed the following:
LDA $0300
STA $2007
LDA $0301
STA $2007
;...
LDA $04FF
STA $2007
JMP saved_PC ;the mapper feeds in the address for the absolute jump
saved_PC: ;continuing off from "STA write_to_2007"
...
If the same mapper also supported sound feed to $4011 (such as Memblers's Squeedo mapper), this unrolled loop generation (for writes to $2004) could also be used as an interrupt-able substitute for sprite DMA. That way, interrupts for writing to $4011 can go smoothly without interference by sprite DMA.