HardWareMan wrote:
I think that the firmware for the controller must be improved in order to correct work management PH2 signal. The old one controls PH2 pin directly wich are may not be compatible with new schematic with oscillator. By the way, you checked for presence of frequency?
I think so,but i don't know how to improved,maybe I can try it.
see the firmware's sourcecode,maybe you can improved it(I use a 1.6mhz quarz).
Code:
// 00000000
// |||____PHI2 1=up,0=down
// ||_____ROMCS 1=up
// |______RW 1=up
//
// BUS_CLOSE = ~(1 << CPU_PHI2)
void cpu_read(uint16_t address, uint16_t length, uint8_t *data)
{
BUS_CONTROL_OUT = BUS_CLOSE;//pulldown CPU_PHI2,other are up
while(length != 0){
uint8_t c = BUS_CLOSE;
direction_write();
address_set(address);
if((address & 0x8000) != 0){
c &= bit_get_negative(CPU_ROMCS);//pulldown CPU_ROMCS
}
c |= 1 << CPU_PHI2;//pullup PHI2
BUS_CONTROL_OUT = c;//execute op
direction_read();
*data = DATABUS_IN;
data += 1;
BUS_CONTROL_OUT = BUS_CLOSE;
address += 1;
length--;
}
direction_write();
}
void cpu_read_6502(uint16_t address, uint16_t length, uint8_t *data)
{
while(length != 0){
uint8_t c = BUS_CLOSE;
//down -> up
direction_write();
address_set(address);
BUS_CONTROL_OUT = c;//execute op
clock_wait(1);//wait 550ns
//phi2 up
c |= (1 << CPU_PHI2);////pullup PHI2
if((address & 0x8000) != 0){
c &= bit_get_negative(CPU_ROMCS);//pulldown CPU_ROMCS
}
BUS_CONTROL_OUT = c;//execute op
direction_read();
clock_wait(1);//wait 550ns
*data = DATABUS_IN;//read data
data += 1;
BUS_CONTROL_OUT = c;//execute op
//phi2 down, bus close
BUS_CONTROL_OUT = BUS_CLOSE;//pulldown CPU_PHI2,other are up
address += 1;
length--;
}
address_set(ADDRESS_CLOSE);
}
/*
NTSC hardware timing
Master clock fsc: 21.4772272 MHz
CPU clock fsc/12: 1.789773MHz
clock per second 12/fsc: 5.58*10**-7 sec, 0.55 us
*/
void cpu_write_6502(uint16_t address, uint16_t length, const uint8_t *data)
{
while(length != 0){
uint8_t control;
address_set(address);
//phi2 down
////pulldown CPU_RW and CPU_PHI2
control = bit_get_negative(CPU_RW) & bit_get_negative(CPU_PHI2);
BUS_CONTROL_OUT = control;
clock_wait(1);//wait 550ns
//phi2 up
if((address & 0x8000) != 0){
control &= bit_get_negative(CPU_ROMCS);//pulldown CPU_ROMCS
}
control |= (1 << CPU_PHI2);//pullup PHI2
BUS_CONTROL_OUT = control;
//data set
DATABUS_OUT = *data;//write data
data++;
clock_wait(1);//wait 550ns
//phi2 down
control &= bit_get_negative(CPU_PHI2);
BUS_CONTROL_OUT = control;
if((address & 0x8000) != 0){
control &= bit_get_negative(CPU_ROMCS);
}
BUS_CONTROL_OUT = control;
//bus close
BUS_CONTROL_OUT = BUS_CLOSE;
clock_wait(1);
address += 1;
length--;
}
address_set(ADDRESS_CLOSE);
}